Verilog - Basics (I)

It is a HARDWARE DESCRIPTION LANGUAGE used to describe digital systems. It allows you to specify the digital systems at various levels of abstraction - Behavior Level, Register Transfer Level (RTL), Gate Level, Switch Level.

Design Styles:
A system, traditionally, can be designed by either Bottom Up or Top Down. Bottom up is where we start with the lowest of modules and add make complex modules from lower modules. This is usually done for smaller electronic circuits but for huge systems the Top Down approach is preferred. Since this allows the flexibility of early testing and easy change of technologies.
The basic Top Down Approach followed is as follows:
Specification ->
High Level Design ->
Low Level Design ->
RTL Coding ->
Functionality Verification -> Gate Level Simulation ->RTL Coding
Logic Synthesis -> Gate Level Simulation ->RTL Coding
Place and Route ->
Fabrication ->
Post Si Validation

Abstractions:
Behavioral:

• System described by Concurrent Algorithms.
• Each Algorithm consists of sequential instructions executed one after other
  
• Functions, Tasks and always blocks are major components

Register Transfer Level:

• Circuit specified by operations involving trasfer of data between registers
• A clock is always used and RTL has strict time bounds

Gate Level:

• Not advisable since there are tools (synthesis tools) that does this. Gate level simulation is done using the output from these tools
• System described by logical links and timing information
• Logic Values used : 0,1,x,z
• Operations: AND, OR, NOT etc

Verilog Semantics:
Module:

• Verilog design consists of inter-connection of modules
• Modules may be an element or collection of lower level design blocks

An example of a simple module would be,

module mux_2_to_1(a,b,out,outbar,sel);
// 'module' keyword starts a module. definition ends in a semicolon
// Comments start with a double slash
input a,b,sel; // ports are defined at the beginning of module
output out, outbar; // direction is given by input, output, inout (bi-directional)

assign out = sel?a:b; // Module behavior expressed. Each line executes parallely and order
assign outbar = ~out;

endmodule

Continuous (Data) Assignment:

• 'assign' keyword used for continuous assignments i.e the right hand side is applied to the left hand side continuously. A simple way to express Combinatorial Logic
  
• Target of Continuous Assignment is a net with Combinatorial Logic .
• Left Side:
• Net (Vector or Scalar / Concatenated or not)
• Right Side:
• Net or Register / Vector or Scalar / Concatenated or not
• Data flow Operators
• Conditional Assignment: (condition)?(value-if-true):(value-if-false)
• Boolean Logic: ~,&,|
• Arithmetic: +,-,*
• Nested Condition:
  
• assign out = s1?(s0?i3:i2):(s0?i1:i0); //4:1 Mux

Gate Level Description:
The same mux if implemented at gate level would look like,

module muxgate(a,b,sel,out,outbar);
input a,b,sel;
output out,outbar;
wire out1,out2,selb;
and a1(out1,sel,a); //
and b1(out2,selb,b);
not n1(selb,sel);
or o1(out,out1,out2);
assign outbar=~out;
endmodule

• Nets represents the connection between hardware elements. 'wire' is the keyword for Nets
• Each module can be instantiated by . details discussed later.
  
• Verilog Library supports basic logic gates as primitives
  
• and or not nand nor xor xnor not buf
• can be extended to multiple inputs.eg: nand n4(out,in1,in2,in3,in4)
• bufif0 and bufif1 are tri-state buffers
• Primitives do not require instance variable eg and(out,in1,in2,in3)
  

Procedural Assignments:
As said earlier each description of the module (or statements) execute parallely and so order is not important (which is very useful in representing Combinatorial Logic) but for implementing Sequential Logic where conditions are executed one after other Procedural Assignments help.

• Two structured procedural statements: initial and always
• Supports richer C-like constructs like if-else, case,for,while

module mux_2_to_1(a,b,out,outbar,sel);
input a,b,sel;
output out,outbar

always @(a or b or sel) begin // always@(sensitivity list) begin execution
if(sel=0) out=a; // the region between begin to end is executed serially and order matters
else out = b;
outbar=~out;
end

endmodule

• Conceptually, always block is called once whenever anything(since 'or' is used) in the sensitivity list is modified.

Verilog Registers:

• Registers (reg) in Verilog corresponds to a variable which can store a value
• Unlike digital system registers (which are memory elements which require clock and so should not be confused) registers do not require clock and value can be changed anytime.

Difference Between Procedural and Continuous Assignments:

• Both can co-exist in the same module
• Procedural statements update a register and this register is not modified unless another procedural statement updates it.
  
• In continuous assignment, the right hand side is constantly placed on the left hand side.

Case Statement:
Case and if may be used interchangeably and Case statements helps in readability in case of long if-else statements.

module mux_2_to_1(a,b,out,outbar,sel);
input a,b,sel;
output out,outbar

always @(a or b or sel) begin
case(sel)
1'b1: a; // number representation '
1'b0: b; // e.g. 16'h4fff - 16 bit hexadecimal value
endcase
outbar=~out;
end

endmodule

N-bit Signals (Vectors) - Power of Verilog:

• Multi-bit signals and buses are easy in Verilog
• 2-to-1 multiplexer with 8-bit operands

module mux_2_to_1(a,b,sel,out,outbar);
input [0:7] a,b;
input sel;
output [0:7] out,outbar;
reg [0:7] out;

always @(a or b or sel) begin
case(sel)
1'b1: a;
1'b0: b;
endcase
outbar=~out;
end

endmodule

• Here 'sel' is a scalar while a,b,out and outbar are called Vectors
• Signals can be concatenated using a Concatenation operator {}
• {b[0:7],b[8:15]} = { a[8:15],a[0:7]}
• The above is a byte swap operation

Integer Arithmetic:
32 bit adder with carry:

module add32(a,b,Cin,out,Cout);
input [0:32] a,b;
input Cin;
output [0:32] out;
output Cout;
assign {Cout,out} = a+b+Cin;
endmodule