Digital Systems (I)

Basic Gate:

• Inverter: out = !in
• MOS gates are like switches. The 'source' is connected to the 'drain' based upon the 'gate' voltage (Vgs).
  
• PMOS: If Vgs
• NMOS: If Vgs>Vt(a threshold voltage), then source and drain are connected else not connected
• CMOS: Complementary MOS i.e combination of a P type and N type MOS. PMOS drain connected to the source of NMOS (and acts as a output). PMOS source connected to Driver Voltage (Vd). NMOS drain connected to the ground. The 'Gate' of both are connected to the 'Input'
  
• CMOS: If Input (Vgs>Vt) PMOS is open and NMOS is closed. So 'Output' connected to 'ground' i.e In = High, Out = Low
• CMOS: If Input (Vgs

Possible functions with two variables:
From the above we can derive the number of functions that are possible with one variable i.e 2. They are Out = In and Out = NOT(In).
Going a step further, lets take two functions.Let 'x' and 'y' be two input variables for a digital system. What are the possible number of functions with x and y?

• x and y each have two states '0' and '1'
• So the possible number of states with both x and y is 2^2 = 4 states.
• So with four possible input states the possible output states is 2^4 (since each state can have 1 or 0) =16 and thus 16 number of functions
  
• In general, for a 'n' input system there are 2^(2^n) functions.

(x y)=> (0,0) (0,1) (1,0) (1,1)<=> (s1,s2,s3,s4)
f(s1,s2,s3,s4)=>(0,0,0,0) (0,0,0,1) (0,0,1,0) (0,0,1,1) ... and so on

Common Gates:
OR(x,y,out)=>(0,0,0)(0,1,1)(1,0,1)(1,1,1) <=> Z = X+Y
AND(x,y,out)=>(0,0,0)(0,1,0)(1,0,0)(1,1,1) <=> Z = X.Y
NOR(x,y,out)=>(0,0,1)(0,1,0)(1,0,0)(1,1,0) <=> Z = NOT(X+Y)
NAND(x,y,out)=>(0,0,1)(0,1,1)(1,0,1)(1,1,0) <=> Z = NOT(X.Y)
XOR(x,y,out)=>(0,0,0)(0,1,1)(1,0,1)(1,1,0) <=> Z = NOT(X).Y + X.NOT(Y)
XNOR(x,y,out)=>(0,0,0)(0,1,0)(1,0,0)(1,1,1) <=> Z = NOT(X).NOT(Y)+X.Y

Generic Gates Design:
CMOS results in inverting functions and so it is usually easier to construct NAND and NOR compared to AND and OR.
As a generalization of the single input case, a gate can be assumed to be designed as PULL UP LOGIC (=> PMOS) and PULL DOWN LOGIC (=> NMOS)
PULL UP => connects the output to Driver Voltage to get high output for required input combination.
PULL DOWN => connects the output to the ground to get Low output for required input combination.
For NAND,
x 0 1 0 1
y 0 0 1 1
Pup on on on off
Pdn off off off on
out 1 1 1 0

For NOR,
x 0 1 0 1
y 0 0 1 1
Pup on off off off
Pdn off on on on
out 1 0 0 0

Boolean Algebra Theorems:

• Elementary
  
• x+0=x <=> x.1=x
• x.0=0 <=> x+1=1
• x+x=x <=> x.x=x
• NOT(NOT(x)) = x
• x+NOT(x)=1 <=> x.NOT(x)=0
• Commutativity
• x+y = y+x <=> x.y=y.x
• Associativity
• x+(y+z) = (x+y)+z <=> x.(y.z) = (x.y).z
• Distributivity
• x.(y+z) = x.y+x.z <=> x+(y.z) = (x+y).(x.z)
• Uniting
• x.y+x.NOT(y) = x <=> (x+y).(x+NOT(y))
• Absorption
• x+x.y=x <=> x.(x+y) = x
• (x+NOT(y)).y = x.y <=> x.NOT(y)+y = (x+y)
• Factoring
• x.y+x.z=x.(y+z) <=> (x+y).(x+z) = x+(yz)
• Consensus
• (x.y)+(y.z)+(NOT(x).z) = (x.y)+(NOT(x).z) <=> (x+y).(y+z).(NOT(x)+z) = (x+y)(NOT(x)+z)
• De Morgan's Law
• NOT(x+y+z+...) = NOT(x).NOT(y)NOT(z)... <=> NOT(x.y.z. ...) = NOT(x)+NOT(y)+NOT(z)+ ...
• Generalised De Morgan's Law
• f(x1,x2,x3..,1,0,.,+) = f(NOT(x1),NOT(x2),NOT(x3)...,0,1,+,.)
• Duality:
• Obtained by replacing exchanging '+' and '.' AND '1' and '0' leaving the variables without any change
• f(x1,x2,x3..,0,1,.,+) <=> f(x1,x2,x3,..,1,0,+,.)